This disclosure relates to electronic circuits, and more particularly, to techniques for storing data and tags in different memory arrays.
In some computing systems, a processor utilizes a memory hierarchy that includes one or more levels of cache memory and a main memory. In an example system, the cache memory stores copies of the data stored in the main memory that are most frequently used by the processor. If most of the memory accesses initiated by the processor are accesses to data stored in memory locations in the cache memory, the average latency of memory accesses is closer to the latency of the cache memory than to the latency of the main memory. When the processor issues a request to read data from a location in the main memory, the processor first determines if a copy of the data is stored in the cache memory. If a copy of the data is stored in the cache memory, the processor reads the data from the cache memory, which is typically faster than reading the data from the main memory.
Implementing a cache memory having a large storage capacity, may result in associated tag circuits for identifying data stored in the cache memory also having a relatively large storage capacity. Thus, the tag circuits may consume a significant amount of die area.